Electronics Lab (Phys2303)
Self-Paced Labs (SPL)

The SPL labs can be turned in at any time during the self-paced part of the course.  The last day to turn in the SPL labs is your last scheduled lab period which is your last lab period the week before the lab practicals begin.

Click here for links to the required software.

Click here for the Basys 3 FPGA pin outs.        [Basys3: Click here for pdf version.]

Manuals. These are a great resource/reference. The manual has diagrams that very clearly describe how the buttons, switches, LEDs, and the 4-digit 7-segment display is wired.
Click here for the Basys3 manual

Click here for the Abacus project source files, required *.vhd modules (LF_clock_source.vhd and nib2led_decoder.vhd), and the Basys3 Master XDC file.
(Right click on the file and select, save target as.. to save the file to your disk.)

Links to "Getting Started Programming" BASYS3

VHDL Language Reference.

Self-Paced Labs (SPL)


Building a 4-Bit Memory
[Module for Lab 16]
{VHDL code example for a D flip-flop}

17 Building a 4-Digit 7-Segment LED Decoder
18 Building a 4-Bit Memory with Hexidecimal Readout
19 Building an 4-Digit Down Counter with Decimal Readout
20 Final Project

Creative Commons License
This work by L.A. Bumm is licensed under a Creative Commons Attribution-NonCommercial-ShareAlike 4.0 International License.