In this example we show how to implement the logical statement from lab 15 problem 4a. The logical inputs are sw0-sw2 and the logical outputs are led0-led3.

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-- Company: University of Oklahoma/Phys2303
-- Engineer: L.A. Bumm
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-- Create Date: 11/06/2016 04:36:40 PM
-- Design Name: 
-- Module Name: lab15_p4a - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
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-- Dependencies: 
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-- Revision:
-- Revision 0.01 - File Created
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity lab15_p4a is
    Port ( sw : in STD_LOGIC_VECTOR (2 downto 0);
           led : out STD_LOGIC_VECTOR (3 downto 0));
end lab15_p4a;

architecture Behavioral of lab15_p4a is

    signal A, B, C, Y : STD_LOGIC;

begin

    A <= sw(0);
    B <= sw(1);
    C <= sw(2);
    Y <= ((not A) and C) or (A and (not B) and (not C));
    led(0) <= sw(0);
    led(1) <= sw(1);
    led(2) <= sw(2);
    led(3) <= Y;

end Behavioral;