Lab 16: Addendum.

A feature observed stating with Xilinx ISE WebPack 10.1 is that it is unhappy connecting the clock input of your DFF to the button. The result is that Xilinx reports an error when you try to generate the programming file. This occurs becasue this signal path will not perform well at high speed. We do not care about this. The work around converts this erro to a warning. After the pins are assigned with PACE. Close PACE. Click on the UCF file in the project, this should allow you to open the UCF file in a text editor. Paste the following line into your UCF file and save it.

NET "BTN0" CLOCK_DEDICATED_ROUTE = FALSE;

The programming file should generate OK, but with a warning.